1. Field of the Invention
The present invention relates to a phase-frequency detector, and more particularly, to a phase-frequency detector capable of reducing dead zone.
2. Description of the Prior Art
In a prior art phase lock loop (PLL), a phase-frequency detector (PFD) is used for detecting the phase and frequency differences between an input signal and a feedback signal. Based on the results of the PFD, a charge pump, a loop filter and a voltage-controlled oscillator (VCO) is used for adjusting the operations of the PLL so that the phase and frequency of the feedback signal matches those of the input signal.
Reference is made to FIG. 1 for a functional diagram of a prior art PLL 100. The PLL 100 includes a PFD 110, a charge pump 120, a loop filter 130, a VCO 140, and a frequency divider 150. The PFD 110 detects the phase and frequency differences between clock signals FIN and FREF and generates corresponding output clock signals UP and DOWN. Based on the output clock signals UP and DOWN, it is determined whether the phase of the clock signal FREF needs to be adjusted in the forward or backward directions. Next, the charge pump 120 generates a corresponding control current signal for the loop filter 130 based on the output clock signals UP and DOWN. The loop filter 130 then generates a corresponding control voltage signal for the VCO 140 based on the control current signal. Last, the VCO 140 generates a corresponding output clock signal FOUT based on the control voltage signal. Meanwhile, the output clock signal FOUT is transmitted to the PFD 110 via the frequency divider 150. Based on the output clock signal FOUT, the frequency divider 150 generates the clock signal FREF so that the frequency of the output clock signal FOUT is a multiple of the frequency of the clock signal FREF. Therefore, the PLL 100 can adjusts the phase of the clock signal FREF until the phase and frequency of the clock signal FIN matches those of the clock signal FREF.
Reference is made to FIG. 2 for a diagram illustrating the output signals of a prior art PFD. In FIG. 2, the vertical axis represents the voltage level VAVG corresponding to the average output signal of the prior art PFD (VAVG equals to the average value of the output clock signals UP and DOWN), and the horizontal axis represents the phase difference ΔΦ between the clock signals FIN and FREF. In the ideal case as illustrated in FIG. 2, the voltage VAVG corresponding to the average output signal of the prior art PFD 110 is proportional to the phase difference ΔΦ. However in actual operations, the PFD has two non-ideal output regions: dead-zone and blind-zone. Dead-zone occurs when the phase difference ΔΦ between the clock signals FIN and FREF is very small. Under these circumstances, the signal rising edges of the clock signals FIN and FREF are very close to each other, and there may not be sufficient time for the output clock signals UP and DOWN to reach the voltage levels corresponding to the phase difference ΔΦ. Therefore, the control voltage signals generated by the charge pump 120 and the loop filter 130 are very small, and the PFD 110 may not be able to adjust the phase difference ΔΦ between the clock signals FIN and FREF accurately. Blind-zone occurs when the phase difference ΔΦ between the clock signals FIN and FREF is a multiple of 2π. Under these circumstances, the reset of the PFD 110 is very close to the rising edge of the signals in the next period, and the PFD 110 may not be able to determine the exact value of the phase difference ΔΦ. A PFD capable of reducing dead-zone and blind-zone can provide good performance. It is also preferable for a PFD to use as few active devices as possible so as to reduce the noise in the PLL.
Reference is made to FIG. 3 for a functional diagram of a prior art PFD 300 using RS flip-flops. The PFD 300 includes two RS flip-flops 310, 320, and an AND gate 330. The RS flip-flops 310 and 320 are edge-triggered flip-flops in which a Q terminal generates corresponding outputs when the signals received at an R terminal and an S terminal are on the rising edge. The S terminals of the RS flip-flops 310 and 320 respectively receive the clock signals FIN and FREF, the R terminals of the RS flip-flops 310 and 320 receive the reset signal FRESET, and the Q terminals of the RS flip-flops 310 and 320 respectively generate the two output signals UP and DOWN of the PFD 300.
Reference is made to FIG. 4 for a diagram illustrating the tri-state operation of the prior art PFD 300. The PFD 300 has three operational states: (1) the output clock signals UP and DOWN both have a low logic level (logic 0); (2) the output clock signal UP has a low logic level and the output clock signal DOWN has a high logic level (logic 1); and (3) the output clock signal UP has a high logic level and the output clock signal DOWN has a low logic level. When the output clock signals UP and DOWN both have a low logic level, the PFD 300 switches to another operational state in which the output clock signal UP has a high logic level and the output clock signal DOWN has a low logic level upon detecting the signal rising edge of the clock signal FIN. Meanwhile, the PFD 300 switches back to the original operational state in which the output clock signals UP and DOWN both have a low logic level upon detecting the rising edge of the clock signal FREF. Similarly, when the output clock signals UP and DOWN both have a low logic level, the PFD 300 switches to another operational state in which the output clock signal UP has a low logic level and the output clock signal DOWN has a high logic level upon detecting the rising edge of the clock signal FREF. Meanwhile, the PFD 300 switches back to the original operational state in which the output clock signals UP and DOWN both have a low logic level upon detecting the rising edge of the clock signal FIN.
Reference is made to FIG. 5 for a circuit diagram of a prior art PFD 500. The PFD 500 includes two pulse generators 512 and 522, two latch circuit 514 and 524, a reset control circuit 510, and inverters 51 and 52. The PFD 500 respectively receives the clock signals FIN and FREF at a first input end and a second input end, and respectively generates the output clock signals UP and DOWN at a first output end and a second output end.
The latch circuits 514 and 524 respectively include inverters 53, 54 and inverters 55, 56. The input end and the output end of the inverter 53 are respectively coupled to the output end and the input end of the inverter 54. The input end and the output end of the inverter 55 are respectively coupled to the output end and the input end of the inverter 56. Therefore, the latch circuits 514 and 524 can provide voltages having a high logic level (logic 1) or a low logic level (logic 0) at the output end.
The reset control circuit 510 includes two P-type metal-oxide semiconductor (PMOS) transistors TRESET, Two N-type metal-oxide semiconductor (NMOS) transistors TISO, an NAND gate 50, and inverters 57, 58. When the output ends of the latch circuits 514 and 524 have a low logic level, the transistor TISO is turned off and the latch circuits 514 and 524 are thus electrically isolated from the pulse generators 512 and 522, respectively. The two input ends of the NAND gate 50 are respectively coupled to the output ends of the latch circuits 514 and 524 via the inverters 57 and 58. When the output ends of the latch circuits 514 and 524 have a low logic level, the NAND gate 50 outputs a reset signal FRESET at the output end for turning on (short-circuiting) the transistor TRESET. Therefore, the output ends of the latch circuits 514 and 524 are reset, thereby having a high logic level.
The pulse generators 512 and 522 each include two NMOS transistors TSTART and TSTOP, and respectively include inverters 59 and 60. The gates of the NMOS transistors TSTART in the pulse generators 512 and 522 are coupled to the first and second input ends of the PFD 500, respectively. The gates of the NMOS transistors TSTOP in the pulse generators 512 and 522 are respectively coupled to the first and second input ends of the PFD 500 via the inverters 59 and 60 for detecting the clock signals FIN and FREF. Since the inverters 59 and 60 are coupled between the gates of the transistors TSTART and TSTOP, the inverters 59 and 60 can provide signal delay for respectively controlling the clock signals generated by the pulse generators 512 and 522.
The prior art PFD 500 provides signal delay for controlling the clock signals generated by the pulse generators 512 and 522 using inverters so that the tri-state illustrated in FIG. 4 can be achieved. However, the intrinsic characteristics of each inverter may vary or deviate from its nominal value due to process variations. Therefore, the prior art PFD may not be able to function efficiently.